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integrated silicon solution, inc. www.issi.com 1 rev. i 08/10/09 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. is61wv5128all/als is61wv5128bll/bls is64wv5128bll/bls 512k x 8 high-speed asynchronous cmos static ram august 2009 description the issi is61wv5128axx and is61/64wv5128bxx are very high-speed, low power, 524,288-word by 8-bit cmos static rams. the is61wv5128axx and is61/64wv5128bxx are fabricated using issi 's high- performance cmos technology. this highly reliable pro - cess coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. the is61wv5128axx and is61/64wv5128bxx operate from a single power supply. the is61wv5128all and is61/64wv5128bll are avail - able in 36-pin 400-mil soj, 36-pin mini bga, and 44-pin tsop (type ii) packages. the is61wv5128als and is61/64wv5128bls are available in 32-pintsop (type i), 32-pin stsop (type i), 32-pin sop and 32-pin tsop (type ii) packages. functional block diagram a0-a18 ce oe we 512k x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 features high speed: (is61/64wv5128all/bll) ? high-speed access time: 8, 10, 20 ns ? low active power: 85 mw (typical) ? low stand-by power: 7 mw (typical) cmos standby low power: (is61/64wv5128als/bls) ? high-speed access time: 25, 35 ns ? low active power: 35 mw (typical) ? low stand-by power: 0.6 mw (typical) cmos standby ? single power supply v d d 1.65v to 2.2v (is61wv5128axx) v d d 2.4v to 3.6v (is61/64wv5128bxx) ? fully static operation: no clock or refresh required ? three state outputs ? industrial and automotive temperature support ? lead-free available
2 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls pin configuration (high speed) (61/64wv5128all/bll) 36 mini bga pin descriptions a0-a18 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 bidirectional ports v d d power gnd ground nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a0 a1 a2 a3 a4 ce i/o0 i/o1 v dd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc a18 a17 a16 a15 oe i/o7 i/o6 gnd v dd i/o5 i/o4 a14 a13 a12 a11 a10 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a0 a1 a2 a3 a4 ce i/o0 i/o1 v dd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc nc nc nc a18 a17 a16 a15 oe i/o7 i/o6 gnd v dd i/o5 i/o4 a14 a13 a12 a11 a10 nc nc nc 44 43 42 41 44-pin tsop (type ii) 1 2 3 4 5 6 a b c d e f g h a0 i/o4 i/o5 gnd v dd i/o6 i/o7 a9 a1 a2 oe a10 nc we nc a18 ce a11 a3 a4 a5 a17 a16 a12 a6 a7 a15 a13 a8 i/o0 i/o1 v dd gnd i/o2 i/o3 a14 36-pin soj
integrated silicon solution, inc. www.issi.com 3 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls pin configuration (low power) (61/64wv5128als/bls) 32-pin tsop (type i), (package code t) 32-pin stsop (type i) (package code h) 32-pin sop 32-pin tsop (type ii) (package code t2) pin descriptions a0-a18 address inputs ce chip enable 1 input oe output enable input we write enable input i/o0-i/o7 input/output v d d power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we a18 a15 v dd a17 a16 a14 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a17 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd a15 a18 we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 v dd
4 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls dc electrical characteristics (over operating range) v d d = 2.4v-3.6v symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C1.0 ma 1.8 v v o l output low voltage v d d = min., i o l = 1.0 ma 0.4 v v i h input high voltage 2.0 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width <10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width <10 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 3.3v + 5% symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C4.0 ma 2.4 v v o l output low voltage v d d = min., i o l = 8.0 ma 0.4 v v i h input high voltage 2 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width <10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width <10 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 1.65v-2.2v symbol parameter test conditions min. max. unit v o h output high voltage v d d = min, i o h = -0.1 ma 1.4 v v o l output low voltage v d d = min, i o l = 0.1 ma 0.2 v v i h input high voltage 1.4 v d d + 0.2 v v i l (1) input low voltage C0.2 0.4 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width <10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width <10 ns). not 100% tested.
integrated silicon solution, inc. www.issi.com 5 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.5 to v d d + 0.5 v v d d v d d relates to gnd C0.3 to 4.0 v t s t g storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 6 pf c i/o input/output capacitance v o u t = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v d d = 3.3v. truth table mode we ce oe i/o operation v d d current not selected x h x high-z i s b 1 , i s b 2 (power-down) output disabled h l h high-z i c c read h l l d o u t i c c write l l x d i n i c c
6 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls operating range ( v d d ) (is61wv5128bll) (1) range ambient temperature v d d (8 n s ) 1 v d d (10 n s ) 1 commercial 0c to +70c 3.3v + 5% 2.4v-3.6v industrial C40c to +85c 3.3v + 5% 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. operating range ( v d d ) (is64wv5128bll) range ambient temperature v d d (10 n s ) automotive C40c to +125c 2.4v-3.6v high speed (is61wv5128all/bll) operating range ( v d d ) (is61wv5128all) range ambient temperature v d d s peed commercial 0c to +70c 1.65v-2.2v 20ns industrial C40c to +85c 1.65v-2.2v 20ns automotive C40c to +125c 1.65v-2.2v 20ns power supply characteristics (1) (over operating range) -8 -10 -20 symbol parameter test conditions min. max. min. max. min. max. unit i c c v d d dynamic operating v d d = max., com. 50 40 40 ma supply current i o u t = 0 ma, f = f m a x ind. 55 45 45 auto. 65 65 typ. (2) 25 i c c 1 operating v d d = max., com. 35 35 30 ma supply current i o u t = 0 ma, f = 0 ind. 40 40 40 auto. 60 60 i s b 1 ttl standby current v d d = max., com. 10 10 10 ma (ttl inputs) v i n = v i h or v i l ind. 15 15 15 ce v i h , f = 0 auto. 30 30 i s b 2 cmos standby v d d = max., com. 7 7 7 ma current (cmos inputs) ce v d d C 0.2v, ind. 10 10 10 v i n v d d C 0.2v, or auto. 20 20 v i n 0.2v , f = 0 typ. (2) 2 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 7 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls power supply characteristics (1) (over operating range) -25 -35 symbol parameter test conditions min. max. min. max. unit i c c v d d dynamic operating v d d = max., com. 20 20 ma supply current i o u t = 0 ma, f = f m a x ind. 25 25 auto. 50 50 typ. (2) 11 i c c 1 operating v d d = max., com. 10 10 ma supply current i o u t = 0 ma, f = 0 ind. 12 12 auto. 20 20 i s b 1 ttl standby current v d d = max., com. 5 5 ma (ttl inputs) v i n = v i h or v i l ind. 7 7 ce v i h , f = 0 auto. 10 10 i s b 2 cmos standby v d d = max., com. 1 1 ma current (cmos inputs) ce v d d C 0.2v, ind. 2 2 v i n v d d C 0.2v, or auto. 10 10 v i n 0.2v , f = 0 typ. (2) 0.2 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. operating range ( v d d ) (is61wv5128bls) (1) range ambient temperature v d d speed commercial 0c to +70c 2.4v-3.6v 25 ns industrial C40c to +85c 2.4v-3.6v 25 ns low power (is61wv5128als/bls) operating range ( v d d ) (is61wv5128als) range ambient temperature v d d s peed commercial 0c to +70c 1.65v-2.2v 35ns industrial C40c to +85c 1.65v-2.2v 35ns automotive C40c to +125c 1.65v-2.2v 35ns operating range ( v d d ) (is64wv5128bls) range ambient temperature v d d s peed automotive C40c to +125c 2.4v-3.6v 35 ns
8 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls ac test loads figure 1. 319 ? 5 pf including jig and scope 353 ? output 3.3v figure 2. z o = 50? 1.5v 50? output p including jig and scope ac test conditions parameter unit unit unit (2.4v-3.6v) (3.3v + 10%) (1.65v-2.2v) input pulse level 0v to 3v 0v to 3v 0v to 1.8v )nput 2iseand all 4imes 6ns 6ns 6ns input and output timing 1.5v 1.5v 0.9v and reference level (v ref ) /utput ,oad 3eeiguresand 3eeiguresand 3eeiguresand
integrated silicon solution, inc. www.issi.com 9 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls read cycle switching characteristics (1) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t r c read cycle time 8 10 ns t a a address access time 8 10 ns t o h a output hold time 2.0 2.0 ns t a c e ce access time 8 10 ns t d o e oe access time 4.5 4.5 ns t h z o e (2) oe to high-z output 3 4 ns t l z o e (2) oe to low-z output 0 0 ns t h z c e (2 ce to high-z output 0 3 0 4 ns t l z c e (2) ce to low-z output 3 3 ns t p u power up time 0 0 ns t p d power down time 8 10 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output load - ing specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage.
10 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls read cycle switching characteristics (1) (over operating range) -20 ns -25 ns -35 ns symbol parameter min. max. min. max. min. max. unit t r c read cycle time 20 25 35 ns t a a address access time 20 25 35 ns t o h a output hold time 2.5 4 4 ns t a c e ce access time 20 25 35 ns t d o e oe access time 8 12 15 ns t h z o e (2) oe to high-z output 0 8 0 8 0 10 ns t l z o e (2) oe to low-z output 0 0 0 ns t h z c e (2 ce to high-z output 0 8 0 8 0 10 ns t l z c e (2) ce to low-z output 3 10 10 ns t p u power up time 0 0 0 ns t p d power down time 20 25 35 ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
integrated silicon solution, inc. www.issi.com 11 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) (ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce = v i l . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) (ce = oe = v i l ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address
12 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls write cycle switching characteristics (1,3) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t w c write cycle time 8 10 ns t s c e ce to write end 6.5 8 ns t a w address setup time 6.5 8 ns to write end t h a address hold from write end 0 0 ns t s a address setup time 0 0 ns t p w e 1 we pulse width (oe = high) 6.5 8 ns t p w e 2 we pulse width (oe = low) 8.0 10 ns t s d data setup to write end 5 6 ns t h d data hold from write end 0 0 ns t h z w e (2) we low to high-z output 3.5 5 ns t l z w e (2) we high to low-z output 2 2 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output load - ing specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. shaded area product in development
integrated silicon solution, inc. www.issi.com 13 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls write cycle switching characteristics (1,2) (over operating range) -20 ns -25 ns -35 ns symbol parameter min. max. min. max. min. max. unit t w c write cycle time 20 25 35 ns t s c e ce to write end 12 18 25 ns t a w address setup time 12 15 25 ns to write end t h a address hold from write end 0 0 0 ns t s a address setup time 0 0 0 ns t p w e 1 we pulse width (oe = high) 12 18 30 ns t p w e 2 we pulse width (oe = low) 17 20 30 ns t s d data setup to write end 9 12 15 ns t h d data hold from write end 0 0 0 ns t h z w e (3) we low to high-z output 9 12 20 ns t l z w e (3) we high to low-z output 3 5 5 ns notes: 1. tes t conditions for is61wv6416ll assume signal transition times of 1.5ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
14 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls ac waveforms write cycle no. 1 (1,2) (ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
integrated silicon solution, inc. www.issi.com 15 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls notes: 1. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v i h . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps write cycle no. 2 (1,2) (we controlled: oe is high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
16 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls data retention waveform (ce controlled) high speed (is61wv5128all/bll) data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 2.0 3.6 v i d r data retention current v d d = 2.0v, ce v d d C 0.2v com. 2 6 ma ind. 8 auto. 15 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (1.65v-2.2v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 1.2 3.6 v i d r data retention current v d d = 1.2v, ce v d d C 0.2v com. 2 6 ma ind. 8 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 1.8v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 17 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls data retention waveform (ce controlled) low power (is61wv5128als/bls) data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 2.0 3.6 v i d r data retention current v d d = 2.0v, ce v d d C 0.2v com. 0.2 1 ma ind. 2 auto. 10 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (1.65v-2.2v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 1.2 3.6 v i d r data retention current v d d = 1.2v, ce v d d C 0.2v com. 0.2 1 ma ind. 2 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 1.8v, t a = 25 o c and not 100% tested.
18 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls ordering information (high speed) commercial range: 0c to +70c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 (8 1 ) is61wv5128bll-10tl tsop (type ii), lead-free note: 1. speed = 8ns for v d d = 3.3v + 5%. speed = 10ns for v d d = 2.4v to 3.6v. industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 (8 1 ) is61wv5128bll-10bi 36-ball mini bga (6mm x 8mm) is61wv5128bll-10bli 36-ball mini bga (6mm x 8mm), lead-free is61wv5128bll-10ti tsop (type ii) is61wv5128bll-10tli tsop (type ii), lead-free is61wv5128bll-10kli 400-mil plastic soj, lead-free note: 1. speed = 8ns for v d d = 3.3v + 5%. speed = 10ns for v d d = 2.4v to 3.6v. industrial range: -40c to +85c voltage range: 1.65v to 2.2v speed (ns) order part no. package 20 is61wv5128all-20bi 36-ball mini bga (6mm x 8mm) is61wv5128all-20ti tsop (type ii) automotive range: -40c to +125c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 is64wv5128bll-10ba3 36-ball mini bga (6mm x 8mm) is64wv5128bll-10bla3 36-ball mini bga (6mm x 8mm), lead-free is64wv5128bll-10cta3 tsop (type ii), copper leadframe is64wv5128bll-10ctla3 tsop (type ii), copper leadframe lead-free
integrated silicon solution, inc. www.issi.com 19 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls ordering information (low power) industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 25 is61wv5128bls-25tli tsop (type ii), lead-free
20 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls note : 5. reference document : jedec spec ms-027. 1. controlling dimension : mm at the seating plane after final test. 3. dimension b2 does not include dambar protrusion/intrusion. 4. formed leads shall be planar with respect to one another within 0.1mm 2. dimension d and e1 do not include mold protrusion . 12/20/2007
integrated silicon solution, inc. www.issi.com 21 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls note : 1. controlling dimension : mm . 2. reference document : jedec mo-207 08/12/2008 package outline
22 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline
integrated silicon solution, inc. www.issi.com 23 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls
24 integrated silicon solution, inc. www.issi.com rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls
integrated silicon solution, inc. www.issi.com 25 rev. i 08/10/09 is61wv5128all/als, is61wv5128bll/bls is64wv5128bll/bls

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